The proposed CDC T&D methodology is validated in a case study, the acquisition electronics of a complex multi-board, multibus, multi-FPGA (nine Xilinx™ xc2v4000–4bf957) system. Identical test patterns (generated to detect static (stuck-at, shorts and open faults) and dynamic (crosstalk) faults) are used in each FPGA. Complete device-to-device communication channels are tested, including transceivers, buses, and board connectors. The underlying principle of the proposed methodology is to embed a CDC test and diagnosis (CDC T&D) structure in each locally synchronous domain. This is not trivial in GALS systems, for which the CDC issue is challenging. Moreover, high resolution diagnosis is obtained, to identify which device(s) and/or communication channel(s) is (are) faulty. The methodology allows design and prototype validation, low maintenance and repair costs, and production / lifetime at-speed test. The purpose of this paper is to present a novel built-in Clock Domain Crossing (CDC) test and diagnosis methodology for Globally Asynchronous, Locally Synchronous (GALS) systems. The results also confirm the effectiveness of the proposed error-recovery scheme in recovering from CDC failures. The results demonstrate high incidence of process variation-induced violation of setup and hold time at the boundary flip-flops, even when synchronizer flip-flops are employed. To quantify the impact of process variations in the transfer of data at clock domain boundaries of multiclock circuits and to validate the proposed error-recovery method, we conducted a series of HSpice simulations using a 45-nm technology. In the proposed method, CDC faults are located using a CDC-fault dictionary, and their impact is masked using post-silicon clock-path tuning. We integrate solutions for detecting and locating CDC faults, and ensuring post-silicon recovery from CDC failures. Even when robust design methods based on synchronizers and design verification techniques are used, process variations can introduce subtle timing problems that affect data transfer across clock-domain boundaries for fabricated chips. Clock-domain crossing (CDC) faults require careful post-silicon testing for multiclock circuits.
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